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R. Alexander, "Employing Radiation Hardness by Design Techniques with Commercial Integrated Circuit Processes", Digital Avionics Systems Conference, 1997, pp. 1-22. 3. E. Boesch, Jr. L. Taylor, "Charge and Interface State Generation in Field Oxides," IEEE Trans. Nucl. , Dec 1984, p. 1273. 4. R. G. P. R. Chavez, "Design Issues for Radiation Tolerant Microcircuits in Space", 1996 NSREC Short Course, Indian Wells, Ca. 5. R. G. M. R. Bailey, M. Williams, "A Scaleable HBD Cell Library for Radiation Tolerant ASICs for Space Applications", GOMAC 2001.

9. A. D. Thesis at the University of Padova, Italy, December 1998. 10. V. P. V. Dressendorfer, Ionizing Radiation Effects in MPS Devices and Circuits. John Wiley & Sons: 1989, pp. 383387. 11. R. N. Coppage, "Field Oxide Inversion Effects in Irradiated CMOS Devices", IEEE Trans. Nucl. , Dec. 1976, pp. 1604-1609. 93 378 N. Nowlin et at 12. T Calin, M. Nicolaidis, R. Velazco, "Upset Hardened Memory Design for Submicron CMOS Technology", IEEE Trans. Nucl. , Dec. 1996, pp. 2874-2878. 13. E. P. V. Dressendorfer, Ionizing Radiation Effects in MPS Devices and Circuits.

V. Osborn, R. Koga, S. C. Mayer, "Application of Hardness-ByDesign Methodology to Radiation-Tolerant ASIC Technologies", IEEE Trans. Nucl. , Dec. 2000, pp. 2334-2341. 7. C. Lacoe, D. Mayer, E. King, "Reliable and Hardened-by-Design (RHBD) Components for Space", presented at 2002 Design Hardening Workshop, Albuquerque, NM. 8. G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, W. Snoeys, "Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects", IEEE Trans.

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An Introduction to Crystal Analysis by Bragg W.


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