By Dirk Stroobandt
The roots of this ebook, and of the hot examine box that it defines, lie within the scaling of VLSI expertise. With gigahertz process clocks and ever accelerating layout and strategy techniques, interconnects became the proscribing issue for either functionality and density. This expanding impression of interconnects at the approach implementation house necessitates new instruments and analytic innovations to help the method dressmaker. With admire to modeling and research, the reaction to interconnect dom inance is evolutionary. Atomistic- and grain-level types of interconnect constitution, and function types at multi-gigahertz working frequencies, jointly advisor the choice of more suitable fabrics and method applied sciences (e. g. , damascene copper wires, low-permittivity dielectrics). formerly in major results (e. g. , mutual inductance) are further into functionality mod els, as older approximations (e. g. , lumped-capacitance gate load versions) are discarded. although, on the system-level and chip making plans point, the required reaction to interconnect dominance is progressive. Convergent layout flows don't require in simple terms allotted RLC line versions, repeater information, unifi cations with extraction and research, and so forth. fairly, matters resembling wiring layer task, and early prediction of the source and function envelope for the process interconnect (in specific, in accordance with statistical types of the procedure interconnect structure), additionally develop into severe. certainly, system-level interconnect prediction has emerged because the enabler of greater interconnect modeling, less costly approach architectures, and extra effective layout technology.
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For these reasons, circuits are normally partitioned by grouping the components into sub-circuits or modules. Sometimes, the design simply is too big to fit in a single chip. In that case, one considers using multi-chip modules and a partitioning step is needed for dividing the entire circuit over the modules. The actual partitioning process considers many factors, such as the size of the modules, number of modules, and number of interconnections between the modules. 7(a) shows the partitioning of the circuit into three modules.
These nets traverse module boundaries and are called external to the modules. These external nets are shared by multiple modules. To make the modules also disjoint with respect to the nets, each external net is divided into subnets (one for each module that shares the net) and each subnet is assigned to one module. This can be seen as the "cutting" of the nets. In most partitioning processes, one tries to minimize the number of nets that have to be "cut". 3)2 such that each module can be seen as a new circuit and can be partitioned further in the same way.
Characterizing Circuits A circuit is generally characterized by a netlist. It lists all components in the circuit and all nets (interconnections) between them. A description is also given of which nets are connected to which terminals of which components. 2), from the circuit level to the system level. In order to compare different circuits to each other. we must be able to characterize them. The characterization parameters that can be immediately obtained from the netIist are the number of components in the circuit, the number of nets, the distribution of the terminals over the components, and the distribution of the terminals over the nets (the net degree).
A Priori Wire Length Estimates for Digital Design by Dirk Stroobandt